Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate, and an oxide liner is thermally grown on the trench walls. The trench is then refilled, such as with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor. After implantation of the substrate is completed, titanium or other silcide is typically formed on the gates and source/drain reunions to reduce sheet resistance in these areas, for increased performance.
A typical method of trench formation comprises initially growing, a pad oxide layer on the substrate, and depositing a barrier nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicone dioxide interface quality. The trench is then refilled with an insulating material, such as silicon dioxide derived from tetraethyl oitlhosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP), and the nitride and pad oxide are stripped of the active areas, to complete the trench isolation structure.
Well implants are then formed by appropriate masking and ion implantation. Subsequently, the surface is cleaned, a gate oxide layer is formed and a polycrystalline silicon layer is deposited and etched to form a gate electrode. Lightly-doped drain (LDD) or other source/drain implants are thereafter formed by appropriate masking and ion implantation. After LDD resist removal, a conformal layer of oxide or nitride is deposited and anisotropically etched to leave spacers along the edges of the gates, which prevent a subsequently applied heavy-dose source/drain implant from completely overlapping the lightly-doped LLD area next to the grates or other shallow source/drain regions. Ion implantation is then conducted to form source/drain regions, with subsequent activation to complete the transistor structure.
A titanium silicide layer is then formed on the gates and source/drain regions, as by sputtering titanium and rapid thermal annealing (RTA). It may be desirable to prevent the silicidation of selected gate and source/drain regions, for example, in order to form a ballast resistor for electrostatic discharge (ESD) protection circuitry. To create unsilicided gate and source/drain regions a thin resistor protective oxide is deposited before sputtering titanium on the substrate. and appropriate portions of the resistor protective oxide are etched away (this step is referred to as the "resistor protect etch"). After the resist is etched and titanium is deposited, the oxide remaining prevents the formation of silicide in the desired areas.
When creating the STI structure, it is considered desirable for the uppermost surface of the substrate to he flush (i.e., co-planar) with the uppermost surface of the oxide filling the trench at the edges of the trench, in order to maximize the performance of the finished device, and to provide a flat topography for subsequent processing steps, particularly photolithographic processing, thereby facilitating the formation of small features with accuracy and increased manufacturing throughput. However as shown in FIG. 1 the interface of the substrate and the oxide 2 typically exhibits what is referred to as a "wrap-around"; that is, a dip 2a is formed in the oxide 2 at the trench edge 1a. Dip 2a is created during the removal of the pad oxide by overetching to ensure complete removal of the pad oxide.
During processing steps performed after gate electrode formation, such as pre-cleaning steps and the resistor protect etch, the oxide at the trench edges is further eroded, effectively increasing the size of the dip 2a. This oxide loss is disadvantageous when it occurs after impurities have been implanted close to the upper surface of the substrate to form junctions; for example, after LDD and source/drain implant steps. As illustrated in FIG. 2, the depth d of such a junction 3 is referenced to the upper exposed surface 1b of the substrate 1 when the junction 3 is formed. The junction 3 follows the contour of the upper exposed surface 1b of the substrate, so the upper surface 1b and the junction 3 are at roughly a constant distance apart.
Thus, any subsequent oxide loss will reduce the distance between part of the junction 3 and the upper exposed surface 1b of the substrate 1. This is illustrated in FIG. 3, where the original oxide surface 2.sub.0) has been eroded to a lower level 2.sub.i, which causes portion 3a of the junction 3 to be closer to the upper exposed surface of the substrate (i.e., at depth d') than it was prior to the unintended oxide removal. since more of the substrate surface is exposed. This unwanted oxide removal and resultant proximity of the junction to the surface 1b causes problems such as junction leakage when metal silicide layer 4 is formed on substrate surface 1b, thereby adversely affecting, device performance.
There exists a need for a semiconductor device and a method of manufacturing a semiconductor device wherein oxide loss at the edges of isolation trenches during post gate processing, is minimized, thereby reducing junction leakage.